1. Field of the Invention
This invention relates to power MOSFET devices and more particularly to an improved design of such devices.
2. Description of Related Art
In current laterally diffused power MOSFETs, the thickness of diffused layers is scaled to eliminate the surface breakdown. However, due to the thinning of the diffused layer, the on-resistance is accordingly increased. The driving current is therefore reduced.
SUMMARY OF THE INVENTION
In accordance with this invention, a metal oxide semiconductor field effect transistor power device with a lightly doped silicon substrate includes a source region and a drain region, the improvement comprises at least one field implanted island region formed along the surface of the oppositely substrate between the source and drain regions with a field oxide region formed above the field implanted region, a dielectric layer and a gate electrode of matching configurations formed over the substrate, and self-aligned source drain regions implanted into the device with external electrodes connected thereto.
Preferably, the substrate is lightly doped P- silicon including an oppositely doped N- well; the field implanted region being a counterdoped region relative to the N- well
an oppositely doped source region in the substrate with respect to the lightly doped substrate substrate comprises a P-substrate, the well comprises an N- well and the counter doped region is doped P; the external electrode connected to the counterdoped region is connected to one end of an inverter; the depth of the counter doped region is within a range from about 3,000 .ANG. to about 5,000 .ANG., the dopant is applied within a range of energies from about 30 keV to about 50 keV, and within a range of doses from about 1E12 cm.sup.-2 to about 1E13 cm.sup.-2 ; the depth of the counter doped island region is within a range from about 3,000 .ANG. to about 5,000 .ANG., the dopant is applied within a range of energies from about 30 keV to about 50 keV, and within a range of doses from about 1E11 cm.sup.-2 to about 5E11 cm.sup.-2 ; the depth of the counter doped region comprises boron dopant ion selected from boron and BF.sub.2 implanted at a preferred energy of 40 keV to provide a far higher level of doping than in the N-wells of the device the islands having a depth within a range from about 3,000 .ANG. to about 5,000 .ANG., the source/drain regions are doped with a preferred dose of about a phosphorus dopant applied within a range of energies from about 30 keV to about 50 keV, and within a range of doses from about 1E15 cm.sup.-2 to about 5E15 cm.sup.-2 ; the source/drain regions are doped with a preferred dose of about a phosphorus dopant applied within a range of energies from about 30 keV to about 50 keV, and within a range of doses from about 1E15 cm.sup.-2 to about 5E15 cm.sup.-2.
Further in accordance with this invention, a method is provided for manufacture of a metal oxide semiconductor field effect transistor device selected from power devices and peripheral devices with a lightly doped silicon substrate,
forming a field implant region in islands in the device by ion implanting P ions into the islands,
forming a field oxide layer and driving in the field implant dopant,
forming a gate oxide on the device,
forming a gate electrode layer on the gate oxide layer,
patterning the gate electrode layer and the gate oxide layer, and
performing a self-aligned source/drain implant into source/drain regions of the device.
Preferably, the device comprises a power device on a P-substrate, the device includes an N- well with a counterdoped P region; the depth of the counter doped region is within a range from about 3,000 .ANG. to about 5,000 .ANG., the dopant is applied within a range of energies from about 30 keV to about 50 keV, and within a range of doses from about 1E12 cm.sup.-2 to about 1E13 cm.sup.-2 ; and the depth of the source/drain regions is within a range from about 3,000 .ANG. to about 5,000 .ANG., the dopant comprising boron is applied within a range of energies from about 30 keV to about 50 keV, and within a range of doses from about 1E12 cm.sup.-2 to about 1E13 cm.sup.-2 ; and the source/drain dopant comprising phosphorus is applied at a range of energies from about 30 keV to about 50 keV, and a range of doses from about 1E15 cm.sup.-2 to about 5E15 cm.sup.-2 ; an external electrode is connected to the counterdoped region, the counterdoped region being connected to one end of an inverter;
Preferably, the device comprises a peripheral device on a P-substrate comprising,
forming P doped field implant regions and then forming FOX regions over the field implant regions,
forming a gate oxide and gate structure between the FOX regions, and
forming self-aligned source/drain regions by ion implanting source/drain dopant into the substrate adjacent to the gate structure; the field implant regions are formed by ion implantation of phosphorus dopant, the dopant being applied within a range of energies from about 100 keV to about 150 keV, and within a range of doses from about 1E12 cm.sup.-2 to about 1E13 cm.sup.-2 ; and the source/drain regions are formed by ion implantation of dopant, the dopant comprising phosphorus applied within a range of energies from about 30 keV to about 50 keV, and within a range of doses from about 1E15 cm.sup.-2 to about 5E13 cm.sup.-2.
In accordance with another aspect of the invention, a metal oxide semiconductor field effect transistor device with a lightly doped silicon substrate including an oppositely doped well and oppositely doped source region and oppositely drain region with respect to the lightly doped substrate, manufactured by the method comprising
implanting at least one counter doped region formed along the surface of the well between the source and drain regions, the counter doped region having an external electrode connected thereto;
the substrate comprises a P-substrate,
the well comprises an N- well and the counterdoped region is doped P,
the external electrode being connected to the counterdoped region is connected to one end of an inverter; and the external electrode connected to the counterdoped region is connected to one end of an inverter.